1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a transistor upon and within a doped polysilicon region a spaced distance above another transistor, wherein a pair of junctions of the transistor have lateral surfaces formed by etching of the polysilicon region.
2. Description of the Related Art
Active devices are well known. They are classified as any device which is not passive. A transistor is but one example of an active device. Transistors are therefore regarded as a basic building block of an integrated circuit. Transistor fabrication typically involves forming source/drain impurity regions (hereinafter "junctions") within a single crystalline silicon substrate and gate conductors spaced from the substrate by a gate dielectric arranged between the junctions. Isolation structures are used to isolate the junctions of a transistor from other active areas employed by an integrated circuit. Isolation structures may comprise shallow trenches etched in the substrate that are filled with a dielectric using chemical vapor deposition. Alternately, isolation structures may comprise local oxidation of silicon ("LOCOS") structures which are thermally grown using, e.g., wet oxidation.
Ion implantation of dopants is primarily used to form junctions. Alternatively, although less often used, the junctions may be formed by diffusion doping. Ion implantation involves placing energetic, charged atoms or molecules directly into the substrate surface. The resulting junctions may be self-aligned between the isolation structures and oxide spacers arranged on opposing sidewall surfaces of the gate conductor and gate dielectric. The number of implanted dopant atoms entering the substrate is more easily controlled using ion implantation. Ion implantation results in junctions having a majority carrier opposite that of the surrounding bulk substrate or well area.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to form relatively small, closely spaced multiple transistors within a single integrated circuit In most core logic areas of an integrated circuit there are logic gates and interconnection between those gates. A substantial portion of the core logic areas involves routing interconnect between gates or enlarging junctions to accommodate mutual connection to those junctions. In either instance, the conventional solution to high density core layout is the occupation of lateral area. Unfortunately, since transistors are generally formed within the silicon-based substrate of an integrated circuit, the number of transistors per integrated circuit is limited by the available lateral area of the substrate. Moreover, transistors cannot employ the same portion of a substrate, and increasing the area occupied by the substrate is an impractical solution to this problem. Thus, packing density of an integrated circuit is somewhat sacrificed by the common practice of forming transistors exclusively within a substrate having a limited amount of area.
Conventional transistor isolation techniques have several drawbacks. The previously mentioned LOCOS structures typically arise by first forming a thermally grown or blanket deposited oxide (i.e., pad oxide) layer across the substrate. A thick layer of silicon nitride is deposited across the oxide layer using chemical vapor deposition. Select portions of the silicon nitride are then removed to expose areas of the silicon-based substrate above which the LOCOS structures are to be formed. The LOCOS structures are thermally grown by oxidizing silicon within the exposed areas. The field oxide grows where no masking nitride exists as well as at the edges of the nitride. Unfortunately, some field oxide also grows under the nitride edges, causing the nitride edges to be lifted upward. Thus, the field oxide may encroach into nearby active device regions. Since active device regions may only be 1.0 micron in width, they might be substantially replaced by an encroaching field oxide.
The encroaching field oxide may also lead to another problem during the subsequent step of forming a conductive contact through an interlevel dielectric to a junction adjacent a LOCOS structure. During contact formation, a portion of the interlevel dielectric must be etched away to form an opening therethrough. Overetching may occur, causing a portion of the encroaching field oxide to be removed. This may expose the substrate region under the junction. Thus, a short may result between the junction and the oppositely doped substrate when a conductive material is deposited into the opening. Another limitation of using LOCOS isolation structures is that the thickness of the thermally grown field oxide in submicron regions of exposed silicon is significantly thinner than that grown in wider spacings. Thin field oxides that result from this effect may have an adverse effect on interconnect capacitances to substrate and on the threshold voltage between junctions spaced apart by a LOCOS structure.
The aforementioned isolation structures formed using a shallow trench etch and fill technique also have several disadvantages. For example, void formation can occur if field oxide is deposited into trenches that are narrower than about 2.0 microns. Inversion of the silicon at the sidewalls of p-type active regions may also occur. Moreover, the deposited field oxide must be etched back so that it remains only within the trench and its top surface is level with the original substrate surface. Planarization of the field oxide may be achieved by applying layers of photoresist across the field oxide and substrate surfaces and then etching the field oxide and resist at the same rate. The planarization etch results in shallow isolation structure profiles which vary among different areas. Furthermore, the resist layer tends to not be perfectly planarized and the field oxide must be overetched to ensure that it is removed from all active areas. Thus, the field oxide is etched below the surface of an active area, exposing a portion of a active area sidewall, thereby leading to undesired edge-parasitic conduction and to a higher electric field in the gate dielectric at the sidewall. The resulting threshold voltage of the corner region where the sidewall meets the gate dielectric is undesirably lower than the interior portion of the active device.
It is therefore desirable that a semiconductor fabrication process be developed for the formation of more densely packed transistors. Such a process would lead to an increase in circuit speed as well as an increase in circuit complexity. Furthermore, it is desirable that a better technique be developed for active region isolation, e.g., isolation of transistors. An isolation technique is needed which would ensure that substantially no current flows between isolated active devices. Moreover, a technique is desired that does not require overetching of the isolation oxide to remove it completely from active regions. Further, it is desirable that the isolation oxide not encroach on active device regions and under junctions, thereby preventing shorting between junction and substrate.